Experimental investigations of corona-discharge oxidation of silicon

As integrated-circuit device dimensions decrease, the importance of having new reliable processes for growing MOS gate oxides becomes more and more evident. Short process times and low process temperatures are desirable features in view of tight thermal budget constraints and the need for precise location of dopants. However, conventional thermal oxidation to grow high quality films usually requires relatively long oxidation times and relatively high temperature. Previous research on negative point (anodic) corona-processed SiO 2 films has shown that the thermal budget incurred using the corona process is much lower than in standard thermal oxidation due to the greatly enhanced oxidation rate. Promising results of low-T corona-processed [Special characters omitted.] 100Å films have shown that the films had physical characteristics comparable to those obtained in thermal oxidation. This research extends the previous work: (a) thin oxides ([Special characters omitted.] 200Å) are processed in order to be potentially more relevant to modern MOS processes, and (b) a more thorough electrical characterization is initiated. Electrical tests show that oxide and interface charges are comparable to thermal oxides. Breakdown characteristics are promising. The boundary between the corona-processed and control regions is found to be severely compromised. Subsequent corona treatments which overlap such boundary regions are found to restore the quality of the oxide. Fourier Transform Infrared (FTIR) Spectroscopy results show that the negative corona films have a different structure from that of thermal oxide films. Electrical tests on positive point (cathodic) corona-processed SiO 2 films show that the electrical quality of the films is much worse than that of standard thermally grown films, grown at a similar temperature. In the interests of growing more-uniform negative-corona SiO 2 films on broader areas of silicon wafers, experiments using multi-point or multi-needle structures were conducted. The enhancement profiles of films grown in both positive and negative cases are simulated using linear-parabolic rate constants, modified to account for the corona curren

Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems

In this paper an efficient high-speed architecture of Gaussian normal basis multiplier over binary finite field GF(2m) is presented. The structure is constructed by using regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. Since the exponents are powers of 2, the modules are implemented by some simple cyclic shifts in the normal basis representation. As a result, the multiplier has a simple structure with a low critical path delay. The efficiency of the proposed structure is studied in terms of area and time complexity by using its implementation on Vertix-4 FPGA family and also its ASIC design in 180nm CMOS technology. Comparison results with other structures of the Gaussian normal basis multiplier verify that the proposed architecture has better performance in terms of speed and hardware utilization

High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves

In this paper high-speed hardware architectures of point multiplication based on Montgomery ladder algorithm for binary Edwards and generalized Hessian curves in Gaussian normal basis are presented. Computations of the point addition and point doubling in the proposed architecture are concurrently performed by pipelined digit-serial finite field multipliers. The multipliers in parallel form are scheduled for lower number of clock cycles. The structure of proposed digit-serial Gaussian normal basis multiplier is constructed based on regular and low-cost modules of exponentiation by powers of two and multiplication by normal elements. Therefore, the structures are area efficient and have low critical path delay. Implementation results of the proposed architectures on Virtex-5 XC5VLX110 FPGA show that then execution time of the point multiplication for binary Edwards and generalized Hessian curves over GF(2163) and GF(2233) are 8.62µs and 11.03µs respectively. The proposed architectures have high-performance and high-speed compared to other works

High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m)

In this paper, by employing the logical effort technique an efficient and high-speed VLSI implementation of the digit-serial Gaussian normal basis multiplier is presented. It is constructed by using AND, XOR and XOR tree components. To have a low-cost implementation with low number of transistors, the block of AND gates are implemented by using NAND gates based on the property of the XOR gates in the XOR tree. To optimally decrease the delay and increase the drive ability of the circuit the logical effort method as an efficient method for sizing the transistors is employed. By using this method and also a 4-input XOR gate structure, the circuit is designed for minimum delay. The digit-serial Gaussian normal basis multiplier is implemented over two binary finite fields GF(2163) and GF(2233) in 0.18μm CMOS technology for three different digit sizes. The results show that the proposed structures, compared to previous structures, have been improved in terms of delay and area parameters